1. Field of the Invention
The present invention relates to layout verification, and particularly relates to layout verification to prevent antenna damage.
2. Description of the Related Art
A metal wiring connected to a gate of a transistor is fabricated by plasma etching. When the metal wiring is plasma-etched, charge occurs, and the charge is stored in the gate of the transistor connected to the metal wiring. As a result, a phenomenon in which a gate oxide film is destroyed and transistor characteristics deteriorate occurs. This phenomenon is called antenna damage because the metal wiring functions as an antenna which accumulates the charge.
As one method to prevent this antenna damage, a reduction in the area of the metal wiring is useful. At a design stage, in order to prevent the antenna damage from occurring, layout verification to prevent the antenna damage is performed. A layout verification method to prevent antenna damage is shown in FIG. 10 of the following Patent Document 1.
(Patent Document 1)
Japanese Patent Application Laid-open No. 2001-282884